From: jacksonharbor@att.net
Date: Sun, 25 Mar 2001 02:10:53 +0000
Subject: Nice new PIC part (long)
Message-Id: <20010325021054.TBWY2454.mtiwmhc21.worldnet.att.net@webmail.worldnet.att.net>



Hello again -

Just had my mind expanded (don't worry, no gray stuff 
spilled out ;) by a concept - actually a new PIC - the 
16F628.

Imagine if our old friend, the 16F84, had twice the 
memory (flash, ram, eeprom) along with extra timers, 
optional internal RC clock, analog comparator inputs,
hardware PWM and a USART!  For $2 less per part in 
single quantities! Same pinout as the 16F84 - 18 pin DIP 
package.

Also, the 16F628 has the ability to use the Mclr and 
oscillator pins as general purpose I/O, so you can get 
up to 3 extra pins!

The 16F627 is similar but has only 1K of program memory -
I see the 16F628 as being the better deal since you only 
save another 43 cents by going to the 16F627 over the 
16F628.

I've only used it a little while - used a free DOS 
programmer software from Germany: Picprog by Martin 
Clausen.  It does the 16F84, the 16F62x and the
16F87x parts.  The hardware is a little more complicated 
than the average pic programmer but it does work well 
for me:

  http://www.rotgradpsi.de/mc/picproge.html

This 16F628 would be the perfect vehicle for someone to
add more features to a fully packed 16F84 project like 
Sig_Gen DDS by Curt, WB2V.

Anyway, here are a few gotchas that I ran into while
porting some code from a 16F84 to 16F628:

1) 16F628 will default to analog comparator inputs on 
port a - need to turn these off in the initialization if 
digital I/O is desired.

2) The include file and processor spec should be changed 
for the 16F628.  This may require an update to the 
latest version of the MPASM (2.7) assembler.  Version 
2.7 is still available as a DOS program but the whole 
multimegabyte MPLAB must be downloaded to extract the   
tiny (300k zipped) DOS assembler and include files.

3) Bank 0 sram starts at 0Ch in the 16F84 and at 20h in 
the 16F628, so the location addresses may have to be 
changed.

4) The LVP (Low Voltage Programming) config bit is set 
as a default from the factory - this may affect the use 
of RB4 (pin 10).  For example, even if RB4 isn't used 
and the programmer sets it as an output in trisb, the 
LVP configuration will override this and the pin will   
appear as an input - this can cause excessive power 
consumption in sleep mode if the pin hasn't been tied to 
ground or VCC (which it might not have been since the 
engineer thought he set the pin as an output).

5) EEDATA and EEADR are now in bank 1, they are in bank 
0 in the 16F84.

6) In the 16F84, the 68 gen purpose registers are mapped 
into bank 1 of memory.  In the 16F628, this isn't the 
case, bank 1 contains new memory except for the top 16 
bytes which are the same in any of the four banks.

7) In the 16F84, the EEIF bit (polled when writing to 
the internal eeprom) is located in EECON1 - in the 
16F628, this bit is now in the PIR1 register with the 
other interrupt flags.  Note that the assembler will NOT 
flag a refernece to EEIF in EECON1 as an error.



Best Regards,

Chuck Olson, WB9KZY
Jackson Harbor Press
http://jacksonharbor.home.att.net/